This is a project to design a CPU using Verilog and an FPGA.
The Yuki CPU is a von-Neumann type CPU, meaning code and data space are seperated. It features an 8 bit data bus and an 24 bit address bus, making it capable of addressing 16 MBytes of memory. It executes intructions by moving data according to its microcode, which makes the instructionset of the CPU easily customizeable. The CPU provides the following registers, operations and flags to the microcode:
Registers:
- R0 – R7 (8 bits wide, general purpose registers)
- X index and Y index (24 bits wide, with dec/inc functions)
- USP and SSP (24 bit wide stack pointers)
- ALU:A and ALU:B (8 bits wide, provide access to ALU)
Operations (entirely 8 bit):
- ADD
- SUB
- AND
- OR
- XOR
- SHR
- SHL
- NOT
Flags:
- EQU (ALU:A == ALU:B)
- CARRY (ALU:A + ALU:B > 255)
- BORROW (ALU:A – ALU:B < 0)
- ZERO (ALU:A == 0)
- NEG (ALU:A[7] == 1)
The CPU also features the possibility to jump conditionally and unconditionally up to 255 bytes back/forward in hardware, reducing program size. Additionally, there are two modes, one for supervisor programs and one for user programs, and the possibilty to hook up to 32 interrupts using an interrupt controller to the CPU.